This invention relates to a logical circuit having a bypass circuit which performs a digital or analog operation and more particularly to a digital logical circuit having a high density of integration and capable of performing logical functions.
Various kinds of logical circuits are interconnected with each other and mounted on a base board such that desired logical functions may be performed. In general, logical circuits are of integrated circuit configuration. Logical circuits are usually tested as follows. Namely, test data or test patterns are previously prepared in manual or automatic mode and the test data or patterns are successively supplied to the logical circuits. The tests are completed by comparing the actual outputs of the logical circuits with the theoretically calculated expected values of the outputs of the logical circuits.
However, as the integration density of a logical circuit becomes high and as the circuit configuration thereof becomes complicated, the fabrication of test patterns for examining the functions of a base board with logical circuits interconnected with one another and mounted thereon becomes more and more difficult. It is generally said that there is a relation such that EQU y=kx.sup.2,
where x is the number of the gates in an integrated circuit to be fabricated and y the time required to fabricate the IC (hereafter the term "integrated circuit" is shortened for brevity as such). This explicitly shows that the increase in the number of gates in the IC, that is, in the complexity of the IC configuration, leads directly to an exponential increase in the time required for the fabrication of test patterns for the IC. Although such a logical circuit as a binary counter performs only simple logical functions, it may assume as many possible states as 2.sup.a if it has a bits. Thus, it is not easy to prepare test patterns for the binary counter and also the test thereof takes a considerable time. Publicity is sometimes given to logical circuits which the makers disclose with their functions and specifications alone but not with concrete equivalent circuits. It is therefore impossible to prepare test patterns for such logical circuits since no equivalent circuit can be deduced from the merely abstract scheme disclosed. The complicated IC is necessarily accompanied by an increase in the cost of fabricating the test patterns therefor or by the difficulty in developing it into an equivalent circuit. And this most often causes the designer to give up the fabrication of test patterns. If even only a piece of a complicated IC is mounted along with other simple ICs on a base board, it becomes difficult to fabricate test patterns for examining the complicated IC and also test patterns for inspecting the ICs adjacent to the complicated one. In a base board with a complicated IC and relatively simple ICs, the logical values of the output of the IC forming the stage just previous to the complicated IC is prevented by the complicated IC from being delivered as the base board output, and the complicated IC prevents the logical values of the output thereof from being set in the IC forming the stage just after the complicated IC.
As described above, a base board having at least a complicated IC, besides other relatively simple ICs, mounted thereon has a drawback that the tests for not only the complicated IC but also the adjacent ICs are difficult.
A technique for individually testing the ICs mounted on a base board is disclosed in, for example, the specification of the U.S. Pat. No. 3,789,205 entitled "Method of Testing MOSFET Planar Boards," R. L. James. According to the testing method invented by James, the ICs adjacent to the complicated IC(s) can be individually tested. However, this method cannot be applied to the test of the functions of the whole system, i.e. integral combination of a multiplicity of ICs.